Organizer and Regional Partners

Joanneum Research
Steirmark
Graz
Sponsors

IEEE

IEEE
SSCS
EDS

Platinum Patron

AMS AG
Infineon
NXP
Graz Technical University

Silver Patrons

AVL
Cadence
Chipdesign
Dialog logo
ECSEL EU logo
Gts logo
Intel logo
Toshiba logo

Bronze Patrons

ECSEL AUSTRIA logo
EVG group
MCL
IV Steiermark

Partner

Graz Tourism

REGISTRATION

Online-Registration is closed now.  Please register on-site at the registration desk at the conference venue Messe Congress Graz.
 

Registration time

Monday 09:00 – 19:00

Tuesday 08:00 – 19:00

Wednesday 08:00 – 19:30

Thursday 08:00 – 18:30

 

Additonal On-Site Registration for Friday (Workshop Day) - Graz Technical University

Friday 08:00 – 18:00

 

General purpose of the conferences

The aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The increasing level of integration for system-on-chip design made available by advances in silicon technology is, more than ever before, calling for a deeper interaction among technologists, device experts, IC designers, and system designers. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

 

ESSCIRC 2015 main topics

Analog Circuits

OP-Amps and instrumentation amplifiers CT and DT filters; SC circuits, Comparators; Nonlinear circuits; Voltage and current references; HV circuits; Nonlinear analog circuits; Digitally assisted analog circuits.

 

Data Converters

Nyquist-rate and oversampling A/D and D/A converters; Sample-hold circuits; Time-to-digital converters; ADC and DAC calibration/error correction circuits.

 

RF and mmWave Building Blocks

RF/IF building blocks like LNAs, mixers, power amplifiers, IF amplifiers; Power detectors; Subsystems for RF, mm-wave and THz design with focus on novel design techniques.

 

Frequency Generation

Modulators/demodulators; VCOs; PLLs; DLLs; Frequency synthesizers; Frequency dividers; Integrated passive components.

 

Wireless and Wireline Systems

Receivers/transmitters/transceivers for wireless/wireline systems Gigabit serial links; Clock and data recovery; Equalization; Advanced modulation systems; Base station and handset applications; TV/radio/satellite receivers and transmitters; Radars.

 

Imagers, MEMS, Medical & Displays

Sensor subsystems and interfaces; Accelerometers; Temperature sensing; Imaging and smart imaging chips; AMOLED; MEMs subsystems; RF MEMs; Implantable electronic ICs; Bio-medical imagers; Bio-MEMs integratedsystems; Lab-on-chip; Organic LED and liquid-crystal-display interface circuits; Flat panel and projection displays.

 

Digital Circuits

Techniques for energy efficient and high performance digital circuits; I/O and inter-chip communication; Reconfigurable digital circuit; Security and encryption circuits; Clocking; Arithmetic building blocks; Memories; Microprocessors; DSPs; Memory interfacing; Bus interfacing; Many core and multirate ICs; 3D integration.

 

Power Management and Energy Scavenging

Energy transducers; Power regulators; DC-DC converters; Energy-scavenging circuits; LDOs Boost-buck-converters; LED drivers; Sequencers and supervisors; Green circuits.

 

CONTACT
Local Scientific Secretariat
JOANNEUM RESEARCH
Forschungsgesellschaft mbH
Leonhardstrasse 59, 8010 Graz, Austria
Phone: +43 316 876 11 90
Mail: essxxrc2015@joanneum.at
Web: www.esscirc-essderc2015.org

 

 


 

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